Theses and Dissertations Collection

The Gate All Around (GAA) Field Effect Transistor (FET) is a type of MOS (Metal Oxide Semiconductor) device that circumvents the problem of the existing FinFET devices and produces effective results on scaling up to 7nm technology node and beyond. The significant benefits of this transistor design are size reduction and increased potential for channel length scaling, which attributes to increased transistor density. However, there are some major challenges, like Short Channel Effects (SCE), which include Subthreshold Slope (SS), Drain Induced Barrier lowering (DIBL), and Gate Induced Drain Leakage (GIDL), that are involved in scaling. This paper mainly focuses on reviewing those challenges by analyzing the TCAD simulation results of two different types of GAA FET devices, Nanosheet (NS) and Nanowire (NW), along with the summary of the effect of the width and radius of NS and NW on the above- mentioned short channel effects. A comparative overview of the impact on a single and stacked device is also discussed.