Microelectronics
MRIC 2007/08
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"Microelectronics"
October 30
Aicha Elshabini - Engineering
Abstract: The trends in electronic products are toward miniaturization and increased circuit density. These trends necessitates high density interconnects. Among the packaging technologies such as laminate, ceramic, and thin film, low temperature cofired ceramics (LTCC) offer an excellent combination of properties for RF/microwave applications as well as for high speed digital products. Some of the key properties include the ability to create three dimensional interconnections with high conductivity, the capability of embedding passives, high thermal conductivity, low dielectric loss, and hermeticity. However, to date many vendors are still primarily using vias larger than 100 microns in diameter. Previous work by the researchers, as well as by others, has demonstrated the ability to form microvias as small as 50 microns in LTCC.
Some limited work has also been reported on the fill process for these vias using primarily silver inks. Optimization of this fill process using both gold and silver inks is critical for the wide spread adoption of microvias in high volume LTCC manufacturing lines. This presentation will report on the capability and process for filling microvia interconnects below 100µm as well as the capabilities for alignment of green tape layers during the stacking operation for both silver and gold conductors. The critical process parameters for mechanically punching and filling 50 and 75 µm vias will be discussed. The impact of punch handling at installation will also be addressed along with the installation of punch tooling. Via quality of the green punched layers addressing the potential for slugs as well as cross sections of fired vias will also presented. The electrical performance of the surface components as well as the embedded microvia connected components has been documented. The 75 µm via geometry resulted in no continuity defects while some isolated failures were associated with the 50 µm geometries. The alignment error of via stacks among the printed layers appears to be less than 25 µm though misalignment on the order of 30 to 50 µm was noted between the unprinted and printed layers.
Aicha Elshabini - Engineering
Abstract: The trends in electronic products are toward miniaturization and increased circuit density. These trends necessitates high density interconnects. Among the packaging technologies such as laminate, ceramic, and thin film, low temperature cofired ceramics (LTCC) offer an excellent combination of properties for RF/microwave applications as well as for high speed digital products. Some of the key properties include the ability to create three dimensional interconnections with high conductivity, the capability of embedding passives, high thermal conductivity, low dielectric loss, and hermeticity. However, to date many vendors are still primarily using vias larger than 100 microns in diameter. Previous work by the researchers, as well as by others, has demonstrated the ability to form microvias as small as 50 microns in LTCC.
Some limited work has also been reported on the fill process for these vias using primarily silver inks. Optimization of this fill process using both gold and silver inks is critical for the wide spread adoption of microvias in high volume LTCC manufacturing lines. This presentation will report on the capability and process for filling microvia interconnects below 100µm as well as the capabilities for alignment of green tape layers during the stacking operation for both silver and gold conductors. The critical process parameters for mechanically punching and filling 50 and 75 µm vias will be discussed. The impact of punch handling at installation will also be addressed along with the installation of punch tooling. Via quality of the green punched layers addressing the potential for slugs as well as cross sections of fired vias will also presented. The electrical performance of the surface components as well as the embedded microvia connected components has been documented. The 75 µm via geometry resulted in no continuity defects while some isolated failures were associated with the 50 µm geometries. The alignment error of via stacks among the printed layers appears to be less than 25 µm though misalignment on the order of 30 to 50 µm was noted between the unprinted and printed layers.
Original url: http://www.uidaho.edu/class/mric/archives/pre-2010/fall2007/elshabini